Modeling and Verification of Analog and Mixed Signal ICs from Concept to Post Layout Simulation

Abstract

Modern analog and mixed signal integrated circuit design requires a structured approach to modeling, simulation, and verification throughout the design flow. This course introduces practical methods for taking an analog or mixed signal IC concept from early functional modeling through schematic level simulation, mixed signal verification, statistical analysis, layout implementation, parasitic extraction, and post layout simulation. Topics include behavioral modeling, real number modeling, VerilogA modeling, SPICE simulation, AMS simulation, PVT analysis, Monte Carlo analysis, sensitivity analysis, parasitic extraction, hierarchical verification, and formal verification concepts for digital control logic and mixed signal interfaces.

The course includes a guided lab component in which attendees work through representative modeling and verification exercises using a real world PDK from an advanced nanometer technology node. These labs are intended to reinforce the lecture material and give attendees practical exposure to the types of decisions and tradeoffs involved in modeling, simulating, and verifying analog and mixed signal integrated circuits before tapeout.

Instructor

Dr. Michael C. Kines is a Research Scientist at The Ohio State University’s ElectroScience Laboratory, where his work focuses on RF, analog, and mixed signal integrated circuit design for communication, sensing, and hardware security applications. He has experience designing and verifying integrated circuits in silicon CMOS technologies, including bulk and FDSOI, as well as compound semiconductor technologies including GaN and GaAs. His technical background includes low noise amplifier design, RF front end circuits, hardware security sensors, true random number generators, and mixed signal circuit implementation.

Prior to his role at Ohio State, Dr. Kines worked at Raytheon, where he contributed to circuit and system level research relevant to defense electronics. He has supported multiple integrated circuit tapeouts across academic, government, and defense focused research programs, with experience spanning schematic simulation, layout implementation, parasitic extraction, post layout simulation, and laboratory test planning. He has also authored recent publications on CMOS low noise amplifier design and microelectronic security sensors.

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.