Practical FPGA Design with VHDL “From First RTL to Working Hardware”

Course Description

From first RTL to working hardware

Short technical briefings are followed immediately by demonstrations, guided exercises, and project milestones.

DAY 1 WEEK 1	Requirements to RTL Targeted digital refresher; AMD (Xilinx) FPGA fabric; Vivado flow; VHDL entities, architectures, signals, processes, and simulation. Build and verify the first project modules.
DAY 2 WEEK 1	VHDL Microarchitecture Combinational and clocked patterns; FSM plus datapath; hierarchy, generics, packages, reset and enable discipline; focused Verilog comparisons. Complete a verified RTL checkpoint.
DAY 3 WEEK 2	RTL to FPGA Memory and DSP inference; selected IP; synthesis and implementation; XDC clocks and pins; utilization and timing review. Integrate the board-level interfaces, program the FPGA, and capture a first ILA trace.
DAY 4 WEEK 2	Timing and Hardware Debug Setup, hold, slack, critical paths, pipelining, async-input synchronizers, reset practice, warnings, and DRC review. Use Vivado ILA to diagnose an injected fault and close a seeded timing violation.
DAY 5 WEEK 3	Integration and Evidence Final system integration, reproducible builds, requirements-to-test traceability, and evidence-based review. Demonstrate the completed project and submit the course evidence package.

COURSE-LONG PROJECT  |  RESILIENT COMMAND-AND-TELEMETRY ENDPOINT Across all five sessions, participants build one FPGA subsystem that receives framed commands over UART, validates them with CRC error detection, tracks status and event history, and recovers cleanly from corrupted or missing frames. They then prove its behavior on live hardware with Vivado ILA, finishing with a working demonstration and a compact evidence package.

What participants take away

Synthesizable VHDL • self-checking testbench • XDC constraints • simulation evidence • utilization and timing reports • FPGA bitstream • ILA capture • requirements-to-test traceability matrix

Delivery model: Days 1–2 in Week 1, Days 3–4 in Week 2, and Day 5 in Week 3. A mandatory pre-course tool, driver, USB/JTAG, board, and repository check protects instructional time; restricted or offline networks are supported with a validated offline bundle.

Platform: One standardized entry-level development board based on an AMD (Xilinx) FPGA, one validated AMD Vivado Design Suite release, and portable VHDL-2008 RTL.