Date/Time
Date(s) - 11/09/2026 - 11/23/2026
12:00 PM - 4:00 PM
Abstract
This 20-hour, hands-on course provides engineers and researchers with a practical introduction to FPGA design using VHDL-2008 and the AMD Vivado Design Suite. Beginning with a targeted review of synchronous digital design and FPGA architecture, participants progress through the complete development flow: translating requirements into RTL microarchitecture, developing modular and synthesizable VHDL, constructing self-checking testbenches, synthesizing and implementing the design, applying fundamental timing and I/O constraints, programming the FPGA, and debugging internal behavior using Vivado ILA. An integrated project evolves throughout the five sessions, allowing participants to apply each concept as they move from initial requirements to verified working hardware. The course emphasizes disciplined design practices, verification, timing awareness, and reproducible implementation evidence.
Course Description
One course. One design. The complete FPGA flow.
Move beyond syntax. Carry one subsystem from a bounded requirement through architecture, VHDL RTL, simulation, synthesis, constraints, timing analysis, FPGA programming, and hardware debug.
| DESIGN | Translate bounded requirements into a cycle-accurate architecture and modular, synthesizable VHDL-2008. |
| VERIFY | Create self-checking testbenches, exercise corner cases, and diagnose behavior through assertions and waveforms. |
| IMPLEMENT | Synthesize, constrain, place and route, program the FPGA, inspect timing and utilization, and debug with Vivado ILA. |
Why this course is different
- Every concept is tied to an evolving course-long FPGA design.
- Guided checkpoints keep the class moving without making progress depend on homework.
- Timing, constraints, reset/synchronization discipline, and hardware debug are core topics—not afterthoughts.
- Participants leave with implementation and verification evidence, not only completed exercises.
Target Audience
Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.
Course Details
12:00 PM – 4:00 PM ET
November 9, 2026 – November 23, 2026 – (Mondays & Tuesdays)
Week 1: Nov 9, 10
Week 2: Nov 16, 17
Week 3: Nov 23
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