Dates
Jan 19, 2026 – Jan 23, 2026
1 Week
Class Days
Monday – Friday
Meeting Times
10:00 AM – 5:00 PM ET
35 Hours | 7 hours of lectures per day
Course Description
Are you a verification engineer ready to elevate your skills and tackle the complexities of modern digital design? This comprehensive course, “Pre-Silicon Verification in practice: From RTL to UVM testbenches”, is tailor-made for you.
Designed to empower verification professionals, this workshop will guide you through the intricacies of the Universal Verification Methodology (UVM). You will gain the practical expertise needed to code UVM testbenches and develop robust stimulus for digital designs.
What you will learn:
- Introduction to Hardware Verification and Coverage Metrics
- Introduction to Verification Planning
- SystemVerilog Foundation:
- A focused overview of SystemVerilog language that underpins UVM, covering the essential language constructs used for RTL design and advanced verification
- UVM Mastery
- A deep dive into UVM principles, topology, and best practices, learning how to structure verification environments, create and run tests, and measure and analyze functional coverage.
- Hands-on lab exercises reinforce lectures and discussion topics for this section.
Course Perquisites
Familiarity with Digital Hardware Design, SystemVerilog, or other Hardware Description Languages Experts from the EDA division of Siemens Digital Industries Software will instruct the course. Siemens Digital Industries Software provides software and services across industry domains, including Electronic Design Automation (EDA), allowing businesses to become more agile, flexible, and adaptable.
Student requirements: Internet access during the entire class
Target Audience
Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.
Registration
Registration is open!
MASSOUD EGHTESSAD
Course Instructor
Massoud Eghtessad – Technical Training Manager – Design Verification
Massoud brings over 15 years of experience in design verification, with a strong focus on Siemens EDA tools and industry best practices. He has delivered technical training to customers worldwide, supporting a wide range of ASIC and FPGA projects. His expertise includes hardware description languages and methodologies, including VHDL, SystemVerilog, and UVM.
Massoud designs and delivers training programs that apply principles of adult learning and effective online instruction. Previously, Massoud served as a Senior Applications Consultant at Synopsys and an ASIC product specialist at Texas Instruments, where he provided tool and methodology support across diverse design and verification flows.
Massoud holds an MS in Computer Engineering from Northeastern University and has achieved Technical Training Certifications, including CompTIA CTT+. Massoud is driven by a passion for coaching customers in the practical application of design and verification technologies.