Pre-Silicon Verification in Practice: From RTL to UVM Testbenches

Abstract

In this course, you will learn how to build a complete UVM testbench from the ground up. The training provides a practical, end-to-end introduction to pre-silicon verification, equipping you with the skills needed to verify RTL designs using SystemVerilog and the Universal Verification Methodology (UVM).

This course will cover the following topics in detail:

• What is Hardware Verification
• Introduction to Verification Plans
• RTL Design and SystemVerilog
• Reusable Test Benches and SystemVerilog Object-Oriented Programming
• Universal Verification Methodology (UVM)

• • Why UVM?
  • Intro to UVM
  • UVM Flow
  • Creating Stimuli and Sequences in UVM
  • UVM Components (Driver, Monitor, Agent, Coverage Collector, Scoreboard, Environment, Test)
  • UVM Configuration and Factory

Course Description

Are you a verification engineer ready to elevate your skills and tackle the complexities of modern digital design? This comprehensive course, “Pre-Silicon Verification in practice: From RTL to UVM testbenches”, is tailor-made for you. Designed to empower verification professionals, this workshop will guide you through the intricacies of the Universal Verification Methodology (UVM). You will gain the practical expertise needed to code UVM testbenches and develop robust stimulus for digital designs.

Target Audience

Designed for U.S. citizens working in the Department of War, Government, or Government-affiliated employees, industry, as well as college students and faculty. Must register with your organizational email, and will be notified of acceptance within one week of the course start date.

Course Details

January 19, 2026 -January 23, 2026

Monday – Friday from 10:00 AM until 5:00 PM ET

Synchronous over Zoom

35 hours | 1 week | 7 hours of lectures per day

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