Full Understanding of the Digital IC Design Flow and the Entire Transformation
Process of Taking the Design from RTL to final bitstream on FPGA and GDSII on
ASIC. The course includes hands on training on FPGA, and final project Tapeout
and fabrication on SKY130.
Digital design flow is a lengthy process that involves many steps to take the design from RTL to
a working silicon. The objective of this course is to demystify this field and provide in-depth
understanding of the different transformations in each design step, how these transformations
can affect the final performance metrics, and how to tune the process to meet design specs.
Specifically, this course focuses on fundamental elements in the design process, including HDL
modeling, event-driven simulation, synthesis, timing analysis, technology files, standard cell
views, physical design, signoff checks, and test planning. Throughout the course, attendees learn
the salient differences in these elements when using FPGA and ASIC platforms. Both Xilinx (for
FPGA) and Cadence (for ASIC) design flows are utilized as part of the training vehicle. VIVADO
from Xilinx to cover the entire FPGA flow. On the Cadence side, ASIC simulations is
demonstrated using Incisive, while Genus is used for synthesis, and Innovus for physical
implementation. Finally, Mentor Graphics’ Calibre is used for ASIC signoff checks. The course
contains a demonstration project, which is progressively developed by the trainees throughout the
course modules to exercise the two digital design flows. The goal of this course is to provide
attendees with understandings of FPGA and ASIC digital flows and to support this understanding
with hands-on experience of tools used by the industry.
Intended Learning Outcomes (ILOs):
Upon the completion of this course, trainees should be able to:
Holistically understand digital design flow (from the specification phase to the signoff
Learn all transformations occur during the design flow and analyze their effect on
Gain knowledge on different technology files and standard cell views.
Identify different design flows based on the target implementation technology (ASIC vs.
Understand timing-analysis and timing-closure in different design phases.
Understand chip level planning (Power Distribution Network, IO, Global Signals, etc).
Design simple digital blocks starting from RTL and taking them to Bitstream or GDSII.
Entry-level design engineers who want to grasp the full digital design cycle, senior undergraduate
and post-graduate students (who are preparing to get involved in digital IC design, research and
development, hardware test), product and verification engineers as well as system and computer
– 32 hours – 8 weeks – 2-hr lectures twice a week
– Module-I: Fundamentals (40%):
o Digital vs Analog.
o Architecture of digital circuits (Delays, data path, control path, synchronization,
o Digital System Design (Microprocessors, FPGA, ASIC).
o Fundamentals of digital design (HDL modeling, synthesis , timing analysis and
timing closure, physical design, chip planning, signoff checks)
o Analyzing and comparing analog vs digital signals over oscilloscopes to
understand the analog side of digital signals (video demonstration).
o Building very simple processor to understand the fundamentals of digital design
and the fundamentals of HDL.
– Module-II: FPGA based design (25%):
o What is an FPGA?
o FPGA fabric architectures.
o HDL modeling and Synthesis for FPGA.
o FPGA types and applications (eFPGAs, Hardware acceleration, ASIC
o Synthesize a simple processor for FPGA and understand the resultant synthesized
HDL and how FPGA bit stream works.
o Detailed comparison between different FPGA fabrics based on vendors and
– Module-III: ASIC design (35%):
o Components of process design kits (PDKs).
o What are standard cells and standard cell views?
o Types of digital synthesis.
o Timing analysis (STA, SSTA).
o Physical design (floorplanning, power planning, Clock Tree Synthesis (CTS), and
o Chip level planning (I/O, power planning, chip testing)
o Signoff checks (DRC, LVS, …)
o Preparing for chip testing, Dos and Don’ts.
o Model a basic processor for ASIC and understand HDL coding style for ASIC vs
o Examine all the files in the design kit/standard cell views and understand the
information provided in each file type.
o Synthesize the processor and understand the different transformations occur with
each design step.
o Implement the physical design and signoff check steps and generate the GDSII of
Throughout the course, trainees will have access to the following computer software:
– Access to VIVADO from Xilinx; Incisive, Genus, Innovus, from Cadence, Modelsim and
Calibre from Mentor Graphics.
– Access to SKY130 (PDK) that includes standard cells library.
– Basic understanding of Digital Logic and Computer Architecture is preferable.
Prof. Eslam Tawfik is currently a research professor at The Ohio State University. His research
topics focus on Digital SoC Design, Hardware Security and Trust, Non Von-Neumann
Architecture, Neuromorphic Computing, Post-Quantum Cryptography, Low-Power Resilient ICs,
Hardware Emulation, and CAD methods. He has solid digital design experience targeting FPGAs
and ASICs, where he worked on different technology nodes to fabricate large number of SoCs. He
also has solid teaching experience in digital design, computer engineering, and computer science
NOTE: This course will take place only on Mondays and Thursdays (from 2-4 pm EST) within the date frame provided.
This event is fully booked.