Dr. Yiorgos Makris, Professor of ECE at the University of Texas at Dallas
In this webinar we will discuss the design of the latest version of our TRAP fabric, the CAD tool-flow necessary for supporting such hybrid designs ASIC/Programmable ICs, and the protection that TRAP-based design redaction offers against both brute-force and intelligent attacks seeking to recover the redacted IP.
Yiorgos is a professor of Electrical and Computer Engineering in the Erik Jonsson School of Engineering & Computer Science at The University of Texas at Dallas, where he leads the Trusted and RELiable Architectures (TRELA) Research Laboratory, the Safety, Security and Health Care Thrust of the Texas Analog Center of Excellence (TxACE), and the UT Dallas site of the NSF Industry University Cooperative Research Center (IUCRC) on Hardware and Embedded System Security and Trust (CHEST). Prior to joining UT Dallas in 2011, he spent 10.5 years as a faculty of Electrical Engineering and of Computer Science at Yale University. He holds a Ph.D. (2001) and an M.S. (1997) in Computer Engineering from the University of California, San Diego, and a Diploma of Computer Engineering and Informatics (1995) from the University of Patras, Greece. His main research interests are in the application of machine learning and statistical analysis in the design of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain. He is also investigating hardware-based malware detection, forensics and reliability methods in modern microprocessors, as well as on-die learning and novel computational modalities using emerging technologies. His research activities have been supported by NSF, ARO, AFRL, KCNSC, SRC, DARPA, Boeing, IBM, LSI, Intel, Advantest, AMS, Qualcomm, and TI.
Yiorgos served as the 2016-2017 general chair and the 2013-2014 program chair of the IEEE VLSI Test Symposium, as well as the 2010-2012 program chair of the Test Technology Educational Program (TTEP). He serves or has served as an associate editor of the IEEE Transactions on Information Forensics and Security, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE Design & Test periodical and the Springer Journal of Electronic Testing: Theory and Applications, and he has also served as a guest editor for the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and as a topic coordinator and/or program committee member for several IEEE and ACM conferences. He is a Senior Member of the IEEE, a recipient of the 2006 Sheffield Distinguished Teaching Award from Yale University, a recipient of Best Paper Awards from the 2013 Design Automation and Test in Europe (DATE’13) conference and the 2015 VLSI Test Symposium (VTS’15), as well as a recipient of Best Hardware Demonstration Awards from the 2016 and 2018 Symposia on Hardware Oriented Security and Trust (HOST’16 and HOST’18).
Bookings are closed for this event.