From Silicon to Systems: The Art of Digital Semiconductor Verification and Software Development

Day 1- Introductions and Demos

From Silicon to Systems: The Art of Digital Semiconductor Verification and Software Development

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Morning:

From Requirements to Systems: a System to Silicon Design Flow Overview (Architecture – Verification – Implementation – Manufacturing)

This morning session explores the complete system design flow for electronic products, from initial concept and requirements gathering to a finished, manufacturable product. We will cover key stages including requirements capture and analysis, system architecture design and partitioning, hardware and software co-design, and implementation. We will include an overview of semiconductor technology, its past and trends – a “Semiconductor 101” – followed by a system design to chip-implementation flow – an “EDA 101.” The course emphasizes practical aspects, covering the topics of architecture analysis, chip-development, software development, verification and digital chip-implementation.

Afternoon

Functional Verification and Software Development: the Verification Continuum flow (Virtual Prototyping, Simulation, Emulation, Prototyping, Early software development)

In this afternoon session, we will explore the various components of the continuum of verification engines from System-level descriptions in SystemC to verified Register-Transfer Level (RTL) descriptions in the Verilog hardware description language (HDL). You will learn about the sweet spots of the different engines, how to use them effectively, and understand how they can be combined to create a comprehensive verification flow. We will cover topics such as simulation, static and formal verification, debug, and verification IP. By the end of this class, you will have a solid understanding of the verification continuum and be able to apply it to your own digital semiconductor designs.

Day 2- Virtualization

From Silicon to Systems: The Art of Digital Semiconductor Verification and Software Development

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Morning:

Early Architecture Exploration & Optimization for Performance and Power

Today’s System-on-Chip (SoC) complexity means spreadsheet-based architecture tools are inefficient and run a high risk of redesign, resulting in higher costs and schedule delay. In this morning session, we will explore how the Synopsys Platform Architect product is used for early system level architecture exploration and optimization for performance and power. Using transaction-level simulation and fast capture of task and trace-based SW workloads, Platform Architect reduces design time by predicting and optimizing architecture key performance indicators (KPIs) like latency, throughput, utilization etc.

This session will include a demonstration of Platform Architect modeling a multi-die design with a compute subsystem, NPX/VPX subsystem and Network-on-chip (NoC). The example will illustrate the workload model, hardware platform and Platform Architect analysis capabilities.

Afternoon:

Virtual Prototyping for Early Software Development and Testing

In this afternoon session, we will explore how Synopsys Virtualizer allows semiconductor designers to perform early software development for semiconductor designs. Integrating increasingly complex hardware and software is a significant challenge for companies developing next-generation wireless, consumer and automotive chips. Traditional methods of developing and verifying software after the silicon design is complete often fail to meet aggressive product development schedules. Virtual prototyping enables software engineers to start development months before the hardware design is complete, enabling full system bring-up to occur within days of silicon availability. Virtual prototypes are fast, fully functional software models of complete systems that execute unmodified production code and provide unparalleled debug efficiency. This session will include a demonstration of Virtualizer, using an Arm based Virtualizer Development Kit (VDK) booting linux. This example will be used to highlight the Transaction Level Model (TLM) Creation, VDK Creation and VDK Debug features.

Day 3 – Functional Verification

From Silicon to Systems: The Art of Digital Semiconductor Verification and Software Development

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Morning:

With the growing complexity of the designs today, verification engineers need to deploy all the tools at their disposal to achieve the goals defined in the verification plan. This session will provide an overview of the different methods to functionally verify IP, Chiplets and Systems-on-Chip (SoC’s) and combine them to provide a unified view of the verification.

In this morning session we will cover the following topics:Dynamic Verification with VCS® covering SystemVerilog and UVM-based testbenches, Verification IP, Register-Transfer Level (RTL) Simulation, coverage models and coverage merging, gate simulation and fault simulation, and debug with Verdi®

Static Verification with VC Spyglass covering Lint Analysis, Clock Domain Crossing Analysis, Reset Domain Crossing Analysis, and debug with Verdi®

Afternoon:

The afternoon session will continue with the following topics:

Continuation of Static Verification

Formal Verification with VC Formal covering Connectivity checking, Formal Coverage Analysis, Sequential Equivalence, and Formal Property Verification Other verification considerations such as low-power verification and equivalence checking.

Day 4 – Hardware Assisted Verification

From Silicon to Systems: The Art of Digital Semiconductor Verification and Software Development

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Morning:

As System-on-Chip (SoC) designs are becoming more complex with ever shrinking time to market needs, digital semiconductor design teams no longer have the luxury of waiting for the first silicon to begin the process of software development. More and more design teams are relying on Hardware Assisted Verification (HAV) to enable early development and validation of the software that will run on the silicon including leveraging the work done in Virtual Prototyping with Virtualizer

In the morning session we will discuss what is Hardware Assisted Verification (HAV), the Synopsys HAV offerings, an overview of emulation with ZeBu® and an overview of prototyping with HAPS®. We will then discuss HAV use cases, integrating real-life interfaces, and explain concept such as the “what and why” of transactors, speed adapters and daughter cards, and how to integrate these into your functional tests.

Afternoon:

In the afternoon session we will continue the discussion by providing an overview of the ZeBu emulation flow. We will cover the compile, runtime and debug flow, as well as system level integration and readiness for emulation. We will show a demo of ZeBu running a PCIe virtual Host solution and a RISCV-based Comet SoC design. We will then provide an overview of the HAPS prototyping flow. We will cover the compile, runtime and debug flow, as well as system level integration and readiness for prototyping. We will show a demo of RISCV Based SOC design prototyped on HAPS platform