Dates
Sep 16, 2024 – Nov 25, 2024
10 Weeks (Federal holiday on 11/11: no classes)
Class Days
Mondays & Thursdays
2x/week
Meeting Times
3:00PM – 5:00 PM
40 Hours
Course Description
Digital design flow is a lengthy process that involves many steps to take the design from RTL to a working silicon. The objective of this course is to demystify this field and provide in-depth understanding of the different transformations in each design step, how these transformations can affect the final performance metrics, and how to tune the process to meet design specs.
Specifically, this course focuses on fundamental elements in the design process, including HDL modeling, event-driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, signoff checks, and test planning. Throughout the course, attendees learn the salient differences in these elements when using FPGA and ASIC platforms. Both Xilinx (for FPGA) and Cadence (for ASIC) design flows are utilized as part of the training vehicle. VIVADO from Xilinx to cover the entire FPGA flow. On the Cadence side, ASIC simulations is demonstrated using Incisive, while Genus is used for synthesis, and Innovus for physical implementation. Finally, Mentor Graphics’ Calibre is used for ASIC signoff checks. The course contains a demonstration project, which is progressively developed by the trainees throughout the course modules to exercise the two digital design flows. The goal of this course is to provide attendees with understandings of FPGA and ASIC digital flows and to support this understanding with hands-on experience of tools used by the industry.
Course Perquisites
Basic understanding of Digital Logic and Computer Architecture is preferable.
Target Audience
DoD, Government or Government Affiliated employees only. Must register with your organizational email and will be notified of acceptance within one week of course start date.
Entry-level design engineers who want to grasp the full digital design cycle, senior undergraduate and post-graduate students (who are preparing to get involved in digital IC design, research and development, hardware test), product and verification engineers as well as system and computer architecture engineers.
Registration
Registration is open!
Prof Eslam Tawfik
Course Instructor
Prof. Eslam Tawfik is currently a research professor at The Ohio State University. His research topics focus on Digital SoC Design, Hardware Security and Trust, Non Von-Neumann Architecture, Neuromorphic Computing, Post-Quantum Cryptography, Low-Power Resilient ICs, Hardware Emulation, and CAD methods. He has solid digital design experience targeting FPGAs and ASICs, where he worked on different technology nodes to fabricate large number of SoCs. He also has solid teaching experience in digital design, computer engineering, and computer science curriculums.
Intended Learning Outcomes (ILOs)
Upon the completion of this course, trainees should be able to:
- Holistically understand digital design flow (from the specification phase to the signoff checks).
- Learn all transformations occur during the design flow and analyze their effect on performance metrics.
- Gain knowledge on different technology files and standard cell views.
- Identify different design flows based on the target implementation technology (ASIC vs. FPGA).
- Understand timing-analysis and timing-closure in different design phases.
- Understand chip level planning (Power Distribution Network, IO, Global Signals, etc).
- Design meaningful digital blocks starting from RTL and taking them to Bitstream or GDSII.
Course Facilities
Throughout the course, trainees will have access to the following computer software:
VIVADO
Xilinx
SKY130 (PDK)
Should include standard cells library.
Incisive
Cadence
Genus
Cadence
Innovus
Cadence
Modelsim
Mentor Graphics
Calibre
Mentor Graphics